FIZZ(10.1) FIZZ(10.1)
NAME
artwork, check, clip, cvt, draw, drills, getparts,
kollmorgen, list, mw, pkgplot, place, prance, ring, signal,
saf, wrap - physical layout programs
SYNOPSIS
cda/artwork [ option ] file ...
cda/check [ -uw ] [ -cchip ] file ...
cda/clip [ -fclipfile ] [ file ... ]
cda/cvt [ file ... ]
cda/draw [ option ] [ file ... ]
cda/drills -ddiams file ...
cda/getparts file ...
cda/kollmorgen [ -hnbx ] file ...
cda/list file ...
cda/mw [ file ... ]
cda/pkgplot [ -bp ] file
cda/place [ file ... ]
cda/prance [ file ... ]
cda/ring [ -lqsuvadk ] [ -zargument ] [ -wargument ] [
-cargument ] file ...
cda/saf [ -sdru ] file ...
cda/signal [ option ] [ file ... ]
cda/wrap [ option ] [ file ... ]
DESCRIPTION
The fizz suite of programs handle all the physical aspects
of creating a wire-wrap, buried micro-via or microwire
board. All the programs take fizz_format(10.6) input;
cdl(10.6) can be converted with cvt.
All of the programs can take multiple files; most of the
programs require that the files form a board description.
Normally, this is arranged amongst four files (with
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FIZZ(10.1) FIZZ(10.1)
recommended suffix): the board and special signal layout
(.brd), the chip, chip type and net descriptions (from
cdmglob(10.1)) (.wx), the package descriptions (.pkg), and
the chip positions (.pos). In general, if the file argu-
ments are missing, standard input is used.
Artwork prints various artwork information for the board
definition in files . The options are
-a prints XY mask clump includes for all placed chips with
artwork fields in their package definitions.
-r prints bounding rectangle information for the microwire
router.
-s generate silk screen information for chip layout.
Check checks the syntax and consistency of the given files.
The -u option causes the names of any unplaced chips to be
printed. Option -w checks readiness for wrapping. Specifi-
cally, it checks that no net is too large; no chip pin coin-
cides with an inappropriate special signal pin, and no chip
pin appears on more than one signal. Option -cchip prints
out detailed information about the named chip.
Clip takes a board description (in files) and a clip
description file (clipfile) and checks that all of and only
the clips specified are present. Clips are simply pins on a
wirewrap board. Almost always they are directly connected
to a signal plane. Clips do not exist in the rest of the
fizz suite; they are simply special signal pins. Standard
input is used if there are no file arguments. The output
reports missing clips in a format suitable as part of a
board description. The clipfile consists of directives (one
per line) of the forms
[ssig|pin] numbers [chip|type] identifiers
tt [chip|type] identifiers
Clips are put on either specific chips with the given names
(chip) or chips of specified chip types (type). The clips
are put on either the specified pins (pin) or pins belonging
to the specified special signals (ssig). The identifier ALL
refers to all chips or types. Lines starting with a % are
ignored. The tt directive means pins whose entry in the tt
field of the type (or the chip's type) is one of GVWXYZ.
For example,
ssig 0,1 type 74F374 74F245
Clips on power and ground for all chips of type 74F374
and 74F245.
pin 3-6,9 chip widget
Clips on pins 3,4,5,6,9 on chip widget.
Numbers are specified as a comma-separated list, possibly
including lo-hi ranges. A missing clipfile argument is
taken as
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FIZZ(10.1) FIZZ(10.1)
tt type ALL
Cvt converts CDL format input and outputs it in
fizz_format(10.6) format. If no files are specified, stan-
dard input is read. Typically, cvt is used to process the
output of cdmglob(10.1). The options are:
-f Don't do families
-c Don't emit comments
-n Don't emit names
Draw generates a plot(6) description of the board layout of
files. Standard input is used if there are no file argu-
ments. The options are
-p Show pins (as circles).
-t Show chip types rather than chip names.
-k Show package names rather than chip names.
-v Show special signal pins as (n+3)-gons where n is the
signal number.
-P Draw package descriptions in pic(1) format. Each draw-
ing shows the package name, the bounding rectangle, a
cross at the origin, and numbered pin locations.
-f Draws the pin frame.
-r Removes the ruler.
Drills takes a board description and a set of drill diame-
ters (diams) and produces a wraplist (like that produced by
wrap) with an entry for every pin whose diameter is in that
set.
Getparts reads its input files and generates a part list on
standard output.
Kollmorgen generates the input files needed for Kollmorgen's
router. Output is to the standard output. The options are
-n Produce nets
-b Produce border (keepouts are also generated). Wiring
area shouldn't be too unusual.
-h Produce holes. Holes may be wired or not depending on
the declaration.
-x Produce correspondence between net names and net num-
bers
List makes a fairly complete parts list giving type, pack-
age, and comment followed by each instance of it with posi-
tion, rotation, and board side. The options are:
-b list burnable parts, like PALs.
-t Special Terry Wallis switch
-s Short output
Mw generates the input for the microwire router for the
board described by files on standard output. Standard input
is used if no file arguments are given.
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Pkgplot generates a plot of the package(s) in the input. the
options are:
-p Generate Postscript
-b Generate bottom up instead of chip down view
Place supports interactive chip placement on a board. It
requires a Plan 9 terminal running 8½. The user interface
is mouse-driven. The main menu items are
select a submenu allowing selecting chips or signals
by name. Signals are displayed in the way
they would be wired by wrap (no -3 support).
view a submenu supporting zooming, panning, grid
overlay and resolution.
insert insert unplaced chips.
place a submenu supporting manual placement,
machine placement and machine improvement of
placement.
read files reset the world and read the given (blank
separated) filenames.
write file write out the chip positions. The filename
conventionally should have a .pos suffix.
exit finito.
Chips can be selected by button 1 or by the button 3 sub-
menu. Selected chips can be edited by the button 2 menu.
Prance generates the input files needed for Cadence's prance
router on standard output.
Ring reads a board description and analyses the Wire 's
therein; these contain the actual route of nets including
all the inflection points. Ring walks each net, and start-
ing from each driver calculates the length of the net (to
the farthest pin). Next, it calculates the gate capacitance
and distributed line capacitance. The rise time of the
driver is used to calculate the maximum length of the line.
Any offending long lines are reported to the user with the
computed impedance of the line.
Saf outputs the packaging data suitable for giving to the
automatic placement machine at Lisle.
Signal gives information about signals in the board descrip-
tion in files. Standard input is used if no file arguments
are given. By default, all signals are shown as sequences
of chip.pin, one signal per line. Note that the lines for
the ground and power signals are likely be very long. The
options are
-w Wrap (route) signals before printing.
-sname
Show the signal name as both chip . pin and board coor-
dinates (one point per line). Unplaced chips have neg-
ative coordinates.
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Wrap generates a wraplist fo rthe board description in
files. The options are
-3 don't do TSP
-n connect to noconnects
-o one post wraps are OK
-v verbosity
-c cents instead of mils
-x don't do wire wraps
-r set root string
-b turn on buried vias
-j produce a .br file suitable for the buried microvia
router
-t make file for cb router
-h produce a .hn file suitable for the buried microvia
router
SEE ALSO
cdl(10.6), mw(10.1), fizz_format(10.6), saf(10.6)
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