INTRO(10.1)                                           INTRO(10.1)

          intro - circuit design aids

          Circuit Design Aids (CDA) is a collection of programs used
          for the design and fabrication of electronic circuits.  CDA
          is composed of programs that communicate through text files.
          A thorough introduction to CDA is given in the document
          "Circuit Design Aids (CDA) on Plan 9".  What follows here is
          an abbreviated version.

        Schematic entry
          Schematics are created with the schematic editor graw(10.1).
          There are three varieties of schematic entities: library
          shapes (for simple gates), boxes of user defined parts and
          wires.  The boxes and library shapes contain the symbolic
          names of pins which will be turned into pin numbers later
          on.  The output of graw is an ASCII file in graw(10.6) for-
          mat.  This must be interpreted by gnet(10.1) to generate a
          net list.  Net lists are combined into a common net list by
          cdmglob(10.1). Cdmglob also expands macros, interprets bus
          notation and matches the symbolic pin names in the schemat-
          ics with the numeric pin numbers in a "pin file" that gives
          the correspondence between symbolic names and numbers in CDL

        Programmable Devices
          Besides commodity parts like the 7400 series, schematics may
          also use programmable devices such as PALs, Actel and Xilinx
          parts.  CDA contains tools that convert logic equations
          written in a language called lde(10.6) format into the vari-
          ous formats required to fry the fuses on a programmable
          device.  Lde format is interpreted by lde(10.1) and gener-
          ates "symbolic product terms".  Programs called "fitters"
          attempt to squeeze lde output into the selected programmable
          part.  Part(10.1), npart(10.1) and xpart(10.1) are the fit-
          ters used for PAL-like devices.  Act(10.1) is the fitter for
          Actel devices.  The output is fed to adil(10.1) which in
          turn must be converted by the Actel software.  The route to
          Xilinx parts is similar.  xil(10.1) generates the intermedi-
          ate format needed by the Xilinx software.

        Physical output
          The output of cdmglob(10.1) has no information about the
          actual physical construction of the circuit.  A separate
          design subsystem of CDA known as fizz does the hard work of
          generating the information needed to build the circuit.
          Cvt(10.1) converts from the CDL output of cdmglob into
          fizz(10.6) format.  Place(10.1) is a graphical tool that
          helps to position parts on the board.  It requires a fizz

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     INTRO(10.1)                                           INTRO(10.1)

          description of the packages, net lists and the board.
          Finally, given the input to fizz and the output of place (a
          position file), wrap(10.1) will generate a wrap file con-
          taining the coordinates of all the wires.

        File naming conventions
          There is a strong convention for naming the files; it is
          highly encouraged but not enforced:

          .g   schematic board description file produced by

          .w   netlist, output from gnet(10.1).

          .cdl circuit description language, output from

          .fx  fizz netlist, output from cvt(10.1).

          .pos chip position file, output of place(10.1).

          .brd board description file including pinholes and special
               signal pins.

          .pkg package definitions.

               pin definitions for input to cdmglob(10.1)

          .lde logic design equations, input to lde(10.1).

          .min minterm(10.6) output from lde(10.1), quine(10.1),
               cover(10.1), or hazard(10.1).

          .adi Actel design intermediate, output from act -a(10.1).

          .adl Actel Design Language, used by Actel software.

          .xy  xymask, the venerable BTL film plotting language.

          .wx  netlist, output from cdmglob(10.1).

          A. G. Hume, M. Kahrs, and T. J. Killian, Circuit Design Aids
          (CDA) on Plan 9

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