GETFCR(2) GETFCR(2)
NAME
getfcr, setfcr, getfsr, setfsr - control floating point
SYNOPSIS
#include <u.h>
#include <libc.h>
ulong getfcr(void)
void setfcr(ulong fcr)
ulong getfsr(void)
void setfsr(ulong fsr)
DESCRIPTION
These routines provide a fairly portable interface to con-
trol the rounding and exception characteristics of IEEE 754
floating point units. In effect, they define a pair of
pseudo-registers, the floating point control register, fcr,
which affects rounding, precision, and exceptions, and the
floating point status register, fsr, which holds the accrued
exception bits. Each register has a get routine to retrieve
its value, a set routine to modify it, and macros that iden-
tify its contents.
The fcr contains bits that, when set, enable exceptions:
FPINEX (enable inexact exceptions), FPOVFL (enable overflow
exceptions), FPUNFL (enable underflow exceptions), FPZDIV
(enable zero divide exceptions), and FPINVAL (enable invalid
operation exceptions). Rounding is controlled by installing
in fcr, under mask FPRMASK, one of the values FPRNR (round
to nearest), FPRZ (round towards zero), FPRPINF (round
towards positive infinity), and FPRNINF (round towards nega-
tive infinity). Precision is controlled by installing in
fcr, under mask FPPMASK, one of the values FPPEXT (extended
precision), FPPSGL (single precision), and FPPDBL (double
precision).
The fsr holds the accrued exception bits FPAINEX, FPAOVFL,
FPAUNFL, FPAZDIV, and FPAINVAL, corresponding to the fsr
bits without the A in the name.
Not all machines support all modes. If the corresponding
mask is zero, the machine does not support the rounding or
precision modes. On some machines it is not possible to
clear selective accrued exception bits; a setfsr clears them
all. The exception bits defined here work on all architec-
tures. By default, the initial state is equivalent to
Page 1 Plan 9 (printed 12/25/24)
GETFCR(2) GETFCR(2)
setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL);
The default state of the floating point unit is fixed for a
given architecture but is undefined across Plan 9: the
default is to provide what the hardware does most effi-
ciently. Use these routines if you need guaranteed behav-
ior. Also, gradual underflow is not available on some
machines.
EXAMPLE
To enable overflow traps and make sure registers are rounded
to double precision (for example on the MC68020, where the
internal registers are 80 bits long):
ulong fcr;
fcr = getfcr();
fcr |= FPOVFL;
fcr &= ~FPPMASK;
fcr |= FPPDBL;
setfcr(fcr);
SOURCE
/sys/src/libc/$objtype/getfcr.s
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